Session: K7-01: THERMOPHYSICAL PROPERTIES I

Paper Number: 138627

138627 - Characterizing Thermal Resistance Across Deeply Buried Interfaces in Advanced Semiconductor Packages 

Abstract: 

High heat fluxes generated in electronic devices must be dissipated by conduction through the semiconductor substrate and packaging layers to avoid local high temperature hotspots that govern device reliability. Particularly, advanced semiconductor packaging configurations (that integrates multiple components within a thin form factor device) increases the need for understanding and improving heat transfer across interfaces. The design of semiconductor packaging solutions is limited by the functionality and accuracy of the metrology techniques available to characterize the thermal resistance of such interfaces buried within the device. In particular, deeply buried interfaces within the semiconductor components are challenging to characterize in situ due to their low relative magnitude and location within the chip stack. This work focuses on the development and experimental demonstration of a novel metrology technique for non-destructive characterization of thermal interfacial resistances within stacks of semiconductor substrates. We target interfaces buried deeper than the thermal penetration depth of available transient measurement techniques, but with thermal resistances below the resolution of most steady state techniques (resistances on the order of 0.01 cm²K/W). The new interfacial conductance measurement technique combines non-contact periodic heating with infrared thermal sensing to measure the transient temperature response of a multi-layer stack of materials. Specifically,  periodic heating of one face and cooling on the opposite phase generates a transient, one-dimensional temperature gradient across the sample stack. The corresponding amplitudes and phase difference of the temperature responses are used to fit for the thermal interfacial resistance, assuming thermal properties of the solid layers are known. To demonstrate and assess the measurement viability, finite element models for a two-layer bonded silicon stack of known thermal properties are leveraged to generate synthetic data for analysis across a range of input parameters. Then, a two-layer bonded sample is experimentally evaluated. The ultimate goal of this work is to develop a standardized technique for measurement of thermal resistances across the range of magnitudes and stack geometries commonly found in modern electronic packages, ranging from near-junction epitaxial semiconductor films to interconnect layers in emerging die-to-die and wafer hybrid bonding technologies.

Presenting Author: Aalok Gaitonde Purdue University

Presenting Author Biography: Aalok develops thermal metrology techniques for advanced semiconductor packaging. Specifically, one of his projects involves developing a novel method to measure the thermal diffusivity of thin heat spreading materials which may have in-plane anisotropy, while another project the aims to develop a metrology tool for the characterization of deeply buried low thermal resistance interfaces found in semiconductor and heterogenous packaging technologies. His research is supported by the Cooling Technologies Research Center (CTRC) and the Semiconductor Research Corporation (SRC). Prior to enrolling in the PhD program, he spent 4 years working with the R&D wing of 3D Systems, developing thermal systems and architecture of Selective Laser Sintering (SLS) additive manufacturing platforms. Aalok completed his master’s degree in mechanical engineering from Purdue University in Fall 2016, where his thesis work included the measurement of thermal conductivity of packed granular beds under the effect of shear and interrogation of the thermal transport and interfaces in lithium-ion batteries.

Authors:

Aalok Gaitonde Purdue University
Justin Weibel Purdue University
Amy Marconnet Purdue University